a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having a high pattern density area with self-aligned contacts and a low pattern density area, and its manufacture method.
b) Description of the Related Art
As semiconductor devices are made highly integrated, fine pattern structures become necessary. Semiconductor memory devices such as dynamic random access memories (DRAMs) are used in the following description as illustrative examples only and not limitatively. In order to increase the memory capacity of a semiconductor memory device, each memory cell is required to be made fine. The peripheral circuit of the semiconductor memory device is not required to be so fine as the memory cell area, but it is necessary to maintain a drive power and a high reliability even at a low power supply voltage. It is therefore desired to form MOS transistors of an LDD structure in the peripheral circuit area.
DRAM memory cells of 2F.times.3F=6F.sup.2 (where F is a minimum design size) are very effective for the reduction of a memory cell area. If the minimum design size is 0.20 to 0.25 .mu.m, use of self-aligned contacts (SACs) of a storage electrode and a bit line is very effective for realizing DRAM of 6F.sup.2 cells.
FIGS. 2A to 2D are schematic diagrams showing the structures of conventional SACs. In FIG. 2A, a field oxide film 102 selectively formed on the surface of a silicon substrate 101 defines an active region AR. A gate oxide film 103 is formed on the silicon surface in the active region AR, and a gate electrode 104 is formed thereon. The field oxide film 102 has a word line WL formed thereon, the word line having the structure same as the gate structure. An insulating film 108 covers the upper surfaces and side walls of the gate electrode 104 and word line WL.
After this substrate structure is formed, an interlayer insulating film is formed over the insulating film 108, with an etching stopper layer being interposed therebetween. A resist mask is formed on the interlayer insulating film and etched to form a SAC window by using as an etching stopper the etch stopper layer on the upper surfaces and side walls of the gate electrode 104 and word line WL. During the SAC window etching process, however, the insulating film on the shoulders of the gate electrode 104 and word line WL is thinned as shown in FIG. 2A and a breakdown voltage of the insulating film lowers at the shoulders.
FIG. 2B shows an example of the SAC structure intended to raise the breakdown voltage at the shoulders of a gate electrode (word line). An insulating film 105 is stacked upon the gate electrode 104 and both of them are patterned using the same mask. Thereafter, an insulating film 108 is formed covering the upper surface and side walls of the laminated gate electrode structure. Since the insulating film 105 is formed on the gate electrode, the breakdown voltage at the shoulder of the gate electrode 104 can be raised.
In a more specific structure, the gate electrode 104 is made of a lamination of a doped amorphous silicon film and a tungsten silicide film, and the insulating film 105 on the gate electrode 104 is made of a lamination of a high-temperature oxide (HTO) film formed by high temperature CVD and an SiON antireflection film formed on the HTO film. This structure has been used in memory cells of 1.0 to 0.5 .mu.m rules.
In the case of memory cells formed with 0.20 to 0.25 .mu.m design rules, however, the height of the capacitor increases in order to provide a sufficient cell capacitance. Therefore, an aspect ratio of the SAC window becomes high. Manufacture of such a high aspect ratio is difficult by the structure shown in FIG. 2B in which the insulating film 105 only is stacked on the gate electrode 104.
FIG. 2C shows an example of the SAC structure suitable for micro patterning. A field oxide film 102 selectively formed on the surface of a silicon substrate 101 defines an active region AR. A gate oxide film 103 formed on the silicon surface in the active region AR has a gate electrode layer 104 formed thereon. The gate electrode layer 104 is made of a lamination of an impurity doped amorphous silicon layer and a tungsten silicide layer formed on the doped amorphous silicon layer. The gate electrode layer 104 has a laminated insulating layer 105a formed thereon. This laminated insulating layer 105a is made of an HTO film, an SiON film serving as an antireflection film and an SiN film serving as an etching stopper. An oxide film 106 covers the surfaces of the gate electrode layer 104 and laminated insulating layer 105a patterned in the same shape.
A nitride film is formed to cover the oxide film 106. This nitride film is anisotropically etched to remove the nitride film formed on the flat surface and leave side spacers 107 of the nitride film only on the side walls of the gate electrode structure. The gate electrode structure is therefore covered with the nitride film of the laminated insulting layer 105a at its upper surface and with the nitride side spacers 107 at its side walls (and at the side walls of a word line WL in the left side of FIG. 2C). An interlayer insulating film 109 of BPSG or the like is formed on this substrate structure.
A resist pattern is formed on the interlayer insulating film 109 which is then anisotropically etched to form an opening between the nitride side spacers 107. In this case, the opening is formed in a self-aligned manner by using the nitride side spacers 107 as the etching stopper. Here, the upper surface of the gate electrode is also covered with the nitride film of the laminated insulating layer 105a, and the nitride film servers as an etching stopper. Thereafter, the oxide film 106 exposed at the bottom of the opening is removed.
With this structure, however, the oxide film 106 is interposed between the nitride film of the laminated insulating film 105a on the gate electrode and the nitride film on the side wall of the gate electrode 104 (word line WL). As shown in the left side of FIG. 2C, if the resist pattern is misaligned and the upper surface of the oxide film 106 is exposed in an etching atmosphere, the exposed oxide film 106 may also be etched. If this oxide film 106 is etched deeply, a breakdown voltage between the electrode embedded in the contact hole and the gate electrode 104 (or the word line WL) lowers, and an electrical short may occur at the worst.
FIG. 2D shows an example of the SAC structure capable of solving the above problem associated with the structure shown in FIG. 2C. With this SAC structure shown in FIG. 2D, a laminated insulating film 105 is formed on a gate electrode 104 and patterned to have the same pattern as the gate electrode (word line). The laminated insulating film 105 is made of a lamination of an HTO film and an SiON film serving as an antireflection film. Thereafter, another HTO film is deposited on the gate electrode structure and anisotropically etched to form side spacers 110. Although side spacers are necessary only in the peripheral circuit area, they are also formed in the memory cell area at the same time.
After the side spacers are formed, a lamination of an HTO film 106 and a nitride film 111 is deposited on the whole surface of the substrate, covering the gate electrode structure. The thickness of the nitride film 111 is set so that it can serve as an etching stopper of an oxide film formed on the nitride film 111. For example, the thickness of the oxide film 106 is about 20 nm and that of the nitride film 111 is 70 nm.
An interlayer insulating film of BPSG or the like is formed on the nitride film 111, and a resist pattern is formed on the interlayer insulating film. The interlayer insulating film is etched by using the resist pattern as an etching mask. This etching of the interlayer insulating film automatically stops at the nitride film 111. Thereafter, the nitride film 111 exposed in the opening is selectively etched and then the oxide film 106 is anisotropically etched to expose the surface of the substrate 101.
If the pattern density of the structure shown in FIG. 2D becomes dense, a space between word lines (gate electrodes) becomes short. The thickness of the side spacer 110 is determined based upon the electrical performance of a transistor of a lightly doped drain structure in the peripheral circuit. The thickness of the nitride film 111 is determined so as to provide a function of an etching stopper. The thickness of the oxide film 106 is determined so that the nitride film 111 does not lower the electrical performance of the transistor.
As the thicknesses of insulating films formed between word lines are limited so as to ensure their essential functions, the width of a recess formed by the nitride film 111 becomes narrow as the pattern density becomes high and the space between word lines becomes short. If the width of the recess becomes narrower than some value, it becomes difficult to sufficiently etch the nitride film and oxide film in the recess after the nitride film is exposed.
This phenomenon is supposed to occur from the following reason. During the etching process of the oxide film such as BPSG formed on the nitride film 111, deposition of process induced substances become dominant if the width of the recess becomes narrower than some extent. Nitride may be deposited and etching the recess of the nitride film 111 becomes difficult.